One type of prior computer system comprises a microprocessor connected to an external cache memory, a system memory, and various peripheral devices residing on a system bus. The microprocessor communicates with the cache memory, system memory, and peripherals through a chip that acts as a memory controller and a bridge to the system bus. The memory controller portion of the chip coordinates data transfers to and from these memory components at the request of the microprocessor or the peripheral devices.
FIG. 1 illustrates a prior art computer system employing a memory controller chip. The microprocessor 110 is coupled to an external cache memory 120 and system memory 130 on a host bus 160. The host bus 160 is connected to a memory controller and bridge chip ("memory controller") 140. A second bus, system bus 170, is connected to the memory controller 140. The memory controller 140 functions as a bridge between microprocessor 110 and bus master 150. Bus master 150 represents a peripheral device that is coupled to the system bus 150. For example, bus master 150 may include devices such as a small computer system interconnect (SCSI) controller, a graphics accelerator, and add-in boards.
The memory controller 140 handles data transfer requests to and from both the microprocessor 110 and the bus master 150. The microprocessor 110 may access either the external cache memory 120 or the system memory 130. The bus master 150 may access the system memory device 130. The memory controller 140 receives a read or write request from either the microprocessor 110 or the bus master 150 and determines if one of the devices is the source or target. The microprocessor issues a read or write request using standard microprocessor timings and the bus master issues a read or write request as defined by the protocol rules for the system bus 170. For instance, the system bus 170 may employ the peripheral component interconnect (PCI) protocol, as described in the PCI Local Bus Specification, Rev. 2.1 (July 1995), available from the PCI Special Interest Group (SIG) in Hillsboro, Oreg.
One type of prior art memory controller 140 includes the following functional blocks: a microprocessor interface 142 for communicating with the microprocessor 110, a cache controller 141 for communicating with the external cache memory 120, a system memory controller 143 for communicating with the system memory 130, and a bus controller 144 for communicating with the system bus 170. These functional components of the memory controller are typically included within one integrated circuit chip. Alternatively, some manufacturers split the functions among more than one chip.
For a typical data read, the memory controller 140 receives read commands from the microprocessor 110 or the bus master 150. The memory controller 140 determines (1) the "source", i.e. the device containing the requested data, and (2) the address within the device at which the data is to be found. When the source is determined to be the system memory 130, the memory controller 140 asserts signals to control the data transfer on the memory bus 180.
Typically, the system memory 130 comprises dynamic random access memory (DRAM). For instance, the system memory 130 may comprise synchronous or asynchronous DRAM. Synchronous DRAMs improve system performance over asynchronous DRAMs, but are typically more expensive. Recently another type of DRAM has been used for computer system platforms. The extended data out (EDO) DRAM theoretically improves system performance at a relatively low cost in comparison to page mode DRAM devices.
Two signals on the memory bus 180 are used to enable the system memory 130 in preparation for a data read. The DRAM is therefore addressed in two stages. First a particular row is addressed, and then a column within the row. A row is accessed by latching an address on the memory bus 180 along with the row address strobe (RAS#) signal. Then, an address within the row is accessed by latching a column address on the memory bus 180 with a column address strobe (CAS#) signal. The row of memory that is accessed by the address latched on the RAS# assertion is often referred to as a "page" of memory. The page is considered open for as long as the RAS# signal is asserted. Depending upon the particular DRAM device used, the page may be of any size. For instance, a typical page may be 2 or 4 Kilobytes.
Computer systems often incur a big performance hit whenever accessing system memory. There is a latency in system memory access time due to assertion and deassertion of the RAS# signal. This is because every time the RAS# signal is asserted, it takes a certain number of clocks for the DRAM page to become available thereafter. Moreover, after the RAS# signal has been deasserted, the RAS# signal must be precharged for a predetermined amount of time before being asserted once again. Therefore, each time the RAS# signal is deasserted, a latency occurs before the RAS# signal may be reasserted.
One type of prior art memory controller attempts to decrease system memory access time by monitoring the activity on the memory bus 180 and correspondingly deasserting the RAS# signal when the memory bus 180 is inactive. Thus, the memory controller pro-actively starts the precharge for a later memory access. However, this method may cause a performance hit when the memory bus 180 becomes inactive in the midst of a burst memory read.
For instance, there are times when the memory bus 180 becomes idle because the system bus 170 is not receiving data fast enough. The memory bus is twice as fast as the system bus 170, since the memory bus is 64 bits wide and the system bus is 32 bits wide. Data must therefore be read from the system memory 130 and stored in a buffer within the memory controller 140. The memory controller 140 then dispatches the data from the buffer to the system bus 170. The memory bus 180 becomes idle when the buffer in the memory controller 140 is full. The page in system memory 130 is then closed in the middle of a read operation.
Another instance wherein the memory bus 180 becomes inactive is when a cache hit occurs and a writeback is performed. The memory controller 140 performs cache snoops in parallel with a read from system memory 130. An internal cache within the microprocessor 110 is snooped, and the external cache memory 120 is snooped. If the snoop determines that a writeback to system memory 130 is necessary, data is written to both the system memory 130 and the system bus 170. The writeback to system memory 130 may occur much faster than the writeback to the system bus 170, causing the memory bus 180 to become idle. The page in system memory 130 is once again closed in the middle of a read operation.
It is therefore desirable to provide a memory controller and method of performing system memory reads that will increase the performance of system memory read operations. It is further desirable to provide a method of keeping a memory page open during burst reads from a bus master. Moreover, it is desirable to provide a memory controller that determines whether to keep a page in system memory open based on activity on the system bus, rather than the memory bus.